The present invention relates in general to an integrated circuit (IC) and, in particular, to using scan chains for applying inputs or receiving outputs from the IC where the scan chains have a functional as well as a test operation.
Due to the ever decreasing geometries in today""s very large scale integration (VLSI) designs, the effects of circuit loading due to wiring capacitance are becoming more and more significant. The decreasing geometry is also resulting in larger numbers of logic gates in designs which necessitate automatic manufacturing test generation techniques. However, these techniques typically add additional test only paths, which can impart many negative characteristics, such as increased loading due to additional circuits processing signals connected to scan chains and additional complexity incurred during wiring signals due to the extra connections and long wire lengths required. These test only paths are typically added during the logic synthesis phase of design and are typically arbitrarily connected.
Another factor complicating VLSI design is what is termed manufacturing test requirements. Since every product must be tested, manufacturers of VLSI impose restrictions which when implemented allow them to maximize throughput in manufacturing testers. One aspect of design which affects tester throughput is the degree of balance within the scan chains of an IC device as scan cycles may be wasted loading and measuring results of short chains while operations are being performed on longer scan chains.
There are other applications where scan chains are used during functional operation of a design. For instance, a design might have a finite state machine which contains a reset state. This reset state then causes a predetermined value to be propagated to all scan elements outside of those comprising the finite state machine. Inverting circuit elements may also be placed in the scan path to allow scan circuit elements to be reset to different values. Other applications where scan chains may have functional operation include an imbedded processor which has a reset operation which causes a known value to propagate through the scan path excepting those scan circuit elements comprising the processor. Since scan chains have functional as well as test applications it has not been possible to optimize these chains using prior art methods since certain scan circuit elements had to maintain their functional connections.
The solution to wiring scan chains in the industry does not move scan elements from the scan chain on which they were originally placed. If as the result of a synthesis a scan chain was threaded around an entire region of the design, then optimizations would just result in some improvement on the scan chain but it may still be threaded around the entire region of the design.
Therefore, there is a need for a method to generate data describing scan chains on an IC, partition the scan chains into balanced scan chain elements and reconnect the scan chain to reduce and optimize the signal loading capacitances resulting from the scan chain paths while maintaining those scan circuit element connections needed functional operation.
The present invention uses an optimization method wherein virtually all the test scan paths of all scan chains are partitioned (discarded) while functional scan chain connections are maintained. The scan circuit elements in the design are then placed, during circuit layout, factoring only the functional interconnections. Attributes are assigned to selected scan circuit elements that define which scan circuit elements are to remain connected, which scan circuit elements may be interchanged within a group and which scan circuit elements are the beginning and end of new scan chains. The scan chain paths are then restored using a nearest neighbor type of algorithm thus ensuring minimal additional wiring capacitances. The method has the ability to regenerate scan chains using scan elements from any scan chain with the same group number as defined by a scan attribute. The method also allows the automatic balancing of the scan chains by placing approximately the same number of scan circuit elements into each new scan chain which is desirable for the manufacturer of the IC.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.